lpetrich
Contributor
RISC-V - is a computer-chip architecture that is the fifth of a series that was released by the labs of the University of California at Berkeley.
Numerous computer instruction-set architectures (ISA's) have come and gone over the decades. The first computers each had their own ISA's, and that made it difficult to port software from one to another. This is rather obvious for "assembly language", a thin layer of abstraction atop an ISA, something used since the early 1950's. In the late 1950's, high-level languages started to be used, and though they improve portability, it is at the expense of writing a back end for each ISA.
In 1964, IBM introduced its System/360 family of computers, a family that shared an architecture. That made software much more portable across that family. This architecture had successors System/370, System/390, and the Z architecture, which IBM still sells. So it's the oldest-running architecture at nearly 60 years.
Other computer makers released families of ISA-sharing computers, and when CPU's on a chip became practical in the 1970's, computer-chip makers did likewise. This led to a proliferation of computer and computer-chip families, with varying amounts of success. The IBM 360/370/390/Z was joined by the DEC VAX, the DEC Alpha, the Motorola 68K, the Intel x86, the Sun SPARC, the HP PA-RISC, the MIPS, the ARM, the POWER/PowerPC, ... the RISC-V is the latest entrant.
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What's RISC? Reduced Instruction Set Computing. Although RISC ISA's can have a lot of instructions, they are simplified, like only accessing main memory with load and store instructions (load-store architecture). To compensate, they often have sizable numbers of "registers", on-chip bits of memory, like 32 instead of the x86's 8.
By comparison, the likes of IBM 360 (3x0?), Moto 68K, and Intel x86 are CISC, Complex Instruction Set Computing, which may try to do more in each instruction. Such instructions may be convenient for an assembly-language programmer, but it's more to implement in the computer hardware itself. But assembly-language programming has become rare, so that is much less of a factor nowadays.
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The RISC-V's ISA's governance is unusual for ISA's. Most others are proprietary, exclusive to one computer maker or chip maker, or else licensed from some ISA owner. The RISC-V ISA is managed by a nonprofit foundation, first the RISC-V Foundation in the US, and later RISC-V International in Switzerland, to avoid tangling with US export laws.
"As of 2019, RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the trademarked compatibility logo."
Chip designs that implement RISC-V can be proprietary, however.
Numerous computer instruction-set architectures (ISA's) have come and gone over the decades. The first computers each had their own ISA's, and that made it difficult to port software from one to another. This is rather obvious for "assembly language", a thin layer of abstraction atop an ISA, something used since the early 1950's. In the late 1950's, high-level languages started to be used, and though they improve portability, it is at the expense of writing a back end for each ISA.
In 1964, IBM introduced its System/360 family of computers, a family that shared an architecture. That made software much more portable across that family. This architecture had successors System/370, System/390, and the Z architecture, which IBM still sells. So it's the oldest-running architecture at nearly 60 years.
Other computer makers released families of ISA-sharing computers, and when CPU's on a chip became practical in the 1970's, computer-chip makers did likewise. This led to a proliferation of computer and computer-chip families, with varying amounts of success. The IBM 360/370/390/Z was joined by the DEC VAX, the DEC Alpha, the Motorola 68K, the Intel x86, the Sun SPARC, the HP PA-RISC, the MIPS, the ARM, the POWER/PowerPC, ... the RISC-V is the latest entrant.
-
What's RISC? Reduced Instruction Set Computing. Although RISC ISA's can have a lot of instructions, they are simplified, like only accessing main memory with load and store instructions (load-store architecture). To compensate, they often have sizable numbers of "registers", on-chip bits of memory, like 32 instead of the x86's 8.
By comparison, the likes of IBM 360 (3x0?), Moto 68K, and Intel x86 are CISC, Complex Instruction Set Computing, which may try to do more in each instruction. Such instructions may be convenient for an assembly-language programmer, but it's more to implement in the computer hardware itself. But assembly-language programming has become rare, so that is much less of a factor nowadays.
-
The RISC-V's ISA's governance is unusual for ISA's. Most others are proprietary, exclusive to one computer maker or chip maker, or else licensed from some ISA owner. The RISC-V ISA is managed by a nonprofit foundation, first the RISC-V Foundation in the US, and later RISC-V International in Switzerland, to avoid tangling with US export laws.
"As of 2019, RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the trademarked compatibility logo."
Chip designs that implement RISC-V can be proprietary, however.