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An idea.

Jarhyn

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So take a minimal Turing-complete processor designed to do radial addressing after some coordinate scheme rather than strict numerical addressing

Add an MMC such that all memory is accessible virtually. This is just to make it extensible.

Add some redundancy (three generals?) to do correction

Every frame, expose the whole memory surface to a randomization event with some probability of randomization P.

The (three generals?) then vote on the true memory and correct.

The processor continues executing.

All memory starts at 0.

Does the system eventually, somewhere, contain a detectable representation of its own architecture?
 

Jarhyn

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So take a minimal Turing-complete processor designed to do radial addressing after some coordinate scheme rather than strict numerical addressing

Add an MMC such that all memory is accessible virtually. This is just to make it extensible.

Add some redundancy (three generals?) to do correction

Every frame, expose the whole memory surface to a randomization event with some probability of randomization P.

The (three generals?) then vote on the true memory and correct.

The processor continues executing.

All memory starts at 0.

Does the system eventually, somewhere, contain a detectable representation of its own architecture?

Bonus points to anyone who figures out why I posted this here.
 

steve_bank

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So take a minimal Turing-complete processor designed to do radial addressing after some coordinate scheme rather than strict numerical addressing

Add an MMC such that all memory is accessible virtually. This is just to make it extensible.

Add some redundancy (three generals?) to do correction

Every frame, expose the whole memory surface to a randomization event with some probability of randomization P.

The (three generals?) then vote on the true memory and correct.

The processor continues executing.

All memory starts at 0.

Does the system eventually, somewhere, contain a detectable representation of its own architecture?

If you are writing scifi don't give up your day job.
 

Jarhyn

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So take a minimal Turing-complete processor designed to do radial addressing after some coordinate scheme rather than strict numerical addressing

Add an MMC such that all memory is accessible virtually. This is just to make it extensible.

Add some redundancy (three generals?) to do correction

Every frame, expose the whole memory surface to a randomization event with some probability of randomization P.

The (three generals?) then vote on the true memory and correct.

The processor continues executing.

All memory starts at 0.

Does the system eventually, somewhere, contain a detectable representation of its own architecture?

If you are writing scifi don't give up your day job.

Maybe instead of levying insults, we can instead discuss that the universe could very well be similar to this construction. Certainly the processor architecture is a bit more multi-threaded, to be sure.

Ask yourself, what would it look like being on the inside of such a system?

What minimal architecture is necessary to yield the result of a system that models its own architecture armed purely with random noise and a model of operation?

Maybe if you can't understand the implications... Well, you retired from your day job a while ago. Maybe you should pick it back up again, you might understand some NEW things.
 

none

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So far the system seems to be a risc chip running minix on a low voltage line.
Maybe @excreationist can weigh in...
 

steve_bank

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The OP is throw spaghettis against the wall and see if any of it sticks. This is the pseudo science forum not science and it is not generally taken seriously.

Begin again defining your terms explicitly. It is not for us to figure out what you mean or think you mean.

1. Hypothesis
.2. Support for hypothesis
3. Conclusion

I know Turing Machines, memory, and processors well. An Intel alum.

'radial addressing after some coordinate scheme rather than strict numerical addressing'

Radial addressing appears to be a memory organization that speeds up memory, sounds like a kind of cross point switch.

Have no clue what strict numerical addressing means. It all boils down to logic regadless of the form of memory.

In the evolution of solid state memory there have been many. Anyone remember bauble memory, the universe must therefore be a bubble. Magnetic core memory. Disk memory, the unnerve must be a disk. Shift register dynamic memory.

Customized memory can take many forms not based in digital logic. There is 'wired OR' and wired 'AND'.

Go ahead, knock my socks off.
 

Jarhyn

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The OP is throw spaghettis against the wall and see if any of it sticks. This is the pseudo science forum not science and it is not generally taken seriously.

Begin again defining your terms explicitly. It is not for us to figure out what you mean or think you mean.

1. Hypothesis
.2. Support for hypothesis
3. Conclusion

I know Turing Machines, memory, and processors well. An Intel alum.

'radial addressing after some coordinate scheme rather than strict numerical addressing'

Radial addressing appears to be a memory organization that speeds up memory, sounds like a kind of cross point switch.

Have no clue what strict numerical addressing means. It all boils down to logic regadless of the form of memory.

In the evolution of solid state memory there have been many. Anyone remember bauble memory, the universe must therefore be a bubble. Magnetic core memory. Disk memory, the unnerve must be a disk. Shift register dynamic memory.

Customized memory can take many forms not based in digital logic. There is 'wired OR' and wired 'AND'.

Go ahead, knock my socks off.

Strict numerical addressing being "address 0x00000000 is the same for all processing units".

Radial addressing would be a relative addressing mode that uses a distance and direction, instead, along whatever dimensions one wishes to assign to the memory.

The question is simple: how big would the system have to scale (and how long would it have to run) for the system to begin to represent its own architecture in ways that repeat the pattern?

It's in the pseudoscience forum because the question applies to what we call a universe.

I wonder to myself "what is the set of such architectures that come to geometric expansion of the reimplementation of their own architecture?"

I call it 'the multiverse of all provable intelligent life'.
 

steve_bank

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Relative addressing is part of all processors. If we are talking memory that stores information then here has to be addressing whatever the form. Otherwise you don't know where the information is.

in C pointers are a form of relative addressing.

When an app is compiled for Windows the addressing is stored as offsets from the start of the app. The executable constrains a symbol table that shows relative offsets of variables from the start. When Windows locates the app at a physical memory location the code executes relative to that location. Relocatable code.

The flip side is absolute code as in embedded processors.
 

steve_bank

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The OP is throw spaghettis against the wall and see if any of it sticks. This is the pseudo science forum not science and it is not generally taken seriously.

Begin again defining your terms explicitly. It is not for us to figure out what you mean or think you mean.

1. Hypothesis
.2. Support for hypothesis
3. Conclusion

I know Turing Machines, memory, and processors well. An Intel alum.

'radial addressing after some coordinate scheme rather than strict numerical addressing'

Radial addressing appears to be a memory organization that speeds up memory, sounds like a kind of cross point switch.

Have no clue what strict numerical addressing means. It all boils down to logic regadless of the form of memory.

In the evolution of solid state memory there have been many. Anyone remember bauble memory, the universe must therefore be a bubble. Magnetic core memory. Disk memory, the unnerve must be a disk. Shift register dynamic memory.

Customized memory can take many forms not based in digital logic. There is 'wired OR' and wired 'AND'.

Go ahead, knock my socks off.

Strict numerical addressing being "address 0x00000000 is the same for all processing units".

Radial addressing would be a relative addressing mode that uses a distance and direction, instead, along whatever dimensions one wishes to assign to the memory.

The question is simple: how big would the system have to scale (and how long would it have to run) for the system to begin to represent its own architecture in ways that repeat the pattern?

It's in the pseudoscience forum because the question applies to what we call a universe.

I wonder to myself "what is the set of such architectures that come to geometric expansion of the reimplementation of their own architecture?"

I call it 'the multiverse of all provable intelligent life'.

Sounds incoherent to me. Non Sequiter.
 

steve_bank

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If there is compatibilism does it follow here is incompatibalism?

Compatibilism sounds like a convoluted way way of saying everything we observe fist together.

How can reality be anything than what it is?
 

Jayjay

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I don't really get the scenario. What's the initial state of the memory? How often does the randomization event occur? Because eventually, there are going to be errors, and the program will no longer function the way it was intended.
 

none

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I don't really get the scenario. What's the initial state of the memory? How often does the randomization event occur? Because eventually, there are going to be errors, and the program will no longer function the way it was intended.
Curious... hmm, does that mean the output would be too random?
 

excreationist

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Probably in a simulation
........Every frame, expose the whole memory surface to a randomization event with some probability of randomization P.

The (three generals?) then vote on the true memory and correct.

The processor continues executing.

All memory starts at 0.

Does the system eventually, somewhere, contain a detectable representation of its own architecture?
If the randomness is strong or widespread enough a "general" wouldn't be able to tell whether there is actually an error or not (like with hamming/parity codes) or what the true memory was. If this happened with two generals at the same time then all three generals would have different answers - and so the randomness would probably be expressed in the simulated world.

If the simulation used "level of detail" then some code works with large-scale behaviour and so there could be large-scale randomness - I'm not sure what issues this would cause exactly....
 

fromderinside

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So take a minimal Turing-complete processor designed to do radial addressing after some coordinate scheme rather than strict numerical addressing

Add an MMC such that all memory is accessible virtually. This is just to make it extensible.

Add some redundancy (three generals?) to do correction

Every frame, expose the whole memory surface to a randomization event with some probability of randomization P.

The (three generals?) then vote on the true memory and correct.

The processor continues executing.

All memory starts at 0.

Does the system eventually, somewhere, contain a detectable representation of its own architecture?
Ah, for the days of threading.
 
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