Steve's post looks a bit lonely, so I'll offer some hand-drawn examples. He shows the primitives of COMBINATORIAL logic. I will show the simplest and most common element of SEQUENTIAL logic -- a one-bit memory, aka a "flip-flop." Three circuits are shown. Each is a flip-flop. (Or rather a "latch", the term preferred back in the day.)
In the first example two NOR gates feed into each other. When both +Set and +Reset are negative (false) the flip-flop remembers its last setting. Activate +Set to force +Q to be true (and -Q negative or false). Activate +Reset for the vice versa.
As shown in the second example you can do the same thing with NAND gates. Or with one AND gate and one OR gate as in the third example.
When I was a circuit designer I worked primarily with TTL and ECL devices, both built from bipolar transistors. The highest speed computers used ECL (NPN). Two anecdotes about those devices may be of interest.
(1) In an ECL OR-gate (or NOR-gate), the inputs connect to the bases of transisters wired in parallel, but in an AND-gate (or NAND-gate) transistors are in series. Thus for the AND-gate a 5.2 volt differential was needed, while about a volt less might suffice if only OR-gates are used. (I write "might suffice" since AFAIK nobody relied on 4.2 volts unless the chip supplier's specs specifically allowed this.) IBM's chips needed only 4.25 volts so the "add-on" people had to route an extra voltage wire to their circuitry -- unless they were using only OR-gates, and Fairchild chips.
Another consequence of the AND-gate internals is that one of the two inputs had about 250 picoseconds of extra margin! I doubt if many designers were perfectionistic enough to take advantage of this.
(2) In the third flip-flop depicted above, the OR-gate is shown as a "Wire-Or." With ECL(NPN) devices, connecting two outputs together provides an OR; no transistors are needed. This can reduce the chip count for a given circuit, and can be convenient for other reasons, but notably
The wire-Or reduces delay. In the example circuit, the input data and the output data are the very same wire -- this is a "zero delay latch"!