RISC-V computer chips

[lpetrich]

 RISC-V - is a computer-chip architecture that is the fifth of a series that was released by the labs of the University of California at Berkeley.

Numerous computer instruction-set architectures (ISA's) have come and gone over the decades. The first computers each had their own ISA's, and that made it difficult to port software from one to another. This is rather obvious for "assembly language", a thin layer of abstraction atop an ISA, something used since the early 1950's. In the late 1950's, high-level languages started to be used, and though they improve portability, it is at the expense of writing a back end for each ISA.

In 1964, IBM introduced its System/360 family of computers, a family that shared an architecture. That made software much more portable across that family. This architecture had successors System/370, System/390, and the Z architecture, which IBM still sells. So it's the oldest-running architecture at nearly 60 years.

Other computer makers released families of ISA-sharing computers, and when CPU's on a chip became practical in the 1970's, computer-chip makers did likewise. This led to a proliferation of computer and computer-chip families, with varying amounts of success. The IBM 360/370/390/Z was joined by the DEC VAX, the DEC Alpha, the Motorola 68K, the Intel x86, the Sun SPARC, the HP PA-RISC, the MIPS, the ARM, the POWER/PowerPC, ... the RISC-V is the latest entrant.

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What's RISC? Reduced Instruction Set Computing. Although RISC ISA's can have a lot of instructions, they are simplified, like only accessing main memory with load and store instructions (load-store architecture). To compensate, they often have sizable numbers of "registers", on-chip bits of memory, like 32 instead of the x86's 8.

By comparison, the likes of IBM 360 (3x0?), Moto 68K, and Intel x86 are CISC, Complex Instruction Set Computing, which may try to do more in each instruction. Such instructions may be convenient for an assembly-language programmer, but it's more to implement in the computer hardware itself. But assembly-language programming has become rare, so that is much less of a factor nowadays.

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The RISC-V's ISA's governance is unusual for ISA's. Most others are proprietary, exclusive to one computer maker or chip maker, or else licensed from some ISA owner. The RISC-V ISA is managed by a nonprofit foundation, first the RISC-V Foundation in the US, and later RISC-V International in Switzerland, to avoid tangling with US export laws.

"As of 2019, RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the trademarked compatibility logo."

Chip designs that implement RISC-V can be proprietary, however.

 

[lpetrich]

RISC-V International - home page
Specifications - RISC-V International

Some of its specs have been ratified by its governing body, some not.

RISC-V comes in 32-bit and 64-bit versions with a possible 128-bit version and a possible compressed-instruction version suitable for embedded duty.

Its base configuration is integer-only with its only arithmetic being addition, subtraction, and shifting, multiplying or dividing by powers of 2. Seems like a throwback to the earliest CPU chips, but that is OK for many embedded applications, where one may not need to do much multiplication -- or much of *any* sort of calculation. In such a case, one can do multiplication and division in software, as repeated addition or subtraction.

It has common RISC features like a load-store architecture and instructions being 4 bytes long and aligned on 4-byte boundaries (32 bits). It has 32 integer registers, with the first one being permanently set to 0. Compressed instructions come in 2-byte chunks (16 bits) and an embedded version may have only 16 registers.

It only has arithmetic operations for 32-bit or 64-bit integers, as the case may be, but it can load and store shorter integers, like 8-bit or 16-bit ones. It also does not have condition flags, bits that indicate whether >0, =0, or <0. A branch instruction would use these flags' values. Instead, it does a comparison before branching.

RISC-V is designed to be extensible, and several extensions are in various stages of discussion and ratification. Each one has a one-letter abbreviation. Here are some ratified ones:

• M - integer multiply and division.
• A - atomic instructions. These execute as one unit, and they are important for communicating between threads.
• F - single-precision (32-bit) floating-point arithmetic.
• D - double-precision (64-bit) floating-point arithmetic.
• Q - quadruple-precision (128-bit) floating-point arithmetic.
• C - compressed instructions.
• G - a general-purpose ISA: M, A, F, D, and some others.

Floating-point instructions would have their own 32 registers.

They have a lot of stuff that they are working on:

• L - decimal floating-point. Good for financial calculations, I'm sure.
• B - bit manipulation, like testing and setting individual bits.
• J - assistance for dynamically-transited programming languages like Java and JavaScript
• T - transactional memory. Being able to update several bits of memory in all-or-nothing fashion, a fail-safety feature common in databases.
• P - packed-SIMD instructions. Several short values in a register, like 8 8-bit or 4 16-bit ones in a 64-bit register.
• V - vector instructions. They operate on several values in sequence.

A RISC-V chip can be run with one or two levels of privilege. One level is good for embedded systems, two for full-scale OSes like Unix-like ones.

RISC-V seems to support having only one memory space, at least at the moment.

 

[lpetrich]

The Wikipedia article has a sizable list of companies that have developed RISC-V chips or are developing such chips.

I was provoked to post on this because of this: Apple Exploring RISC-V, Hiring RISC-V 'High Performance' Programmers | Tom's Hardware

Apple is in the process of switching its PCs to Arm-based SoCs, but the company might not be putting all its eggs into one basket, as it is also exploring the emerging open-source RISC-V architecture. This week the company posted a job alert for RISC-V high-performance programmer(s).

Apple is currently looking for experienced programmers with detailed knowledge of the RISC-V Instruction Set Architecture (ISA) and Arm's Neon vector ISA for its Vector and Numerics Group (VaNG) within its Core Operating Systems group. Apple's VaNG is responsible for developing and improving various embedded subsystems running on iOS, macOS, watchOS, and tvOS.

Apple's job posting: RISC-V High Performance Programmer - Careers at Apple - "The successful candidate will have excellent understanding and knowledge of RISC-V ISA architecture along with working knowledge of NEON micro architecture in ARM CPU cores from a vector programming perspective."

This suggests that Apple is already working on RISC-V: "You will work in a SW and HW cross functional team which is implementing innovative RISC-V solutions and state of the art routines. This is to support the necessary computation for such things as machine learning, vision algorithms, signal and video processing."

A reason for interest in RISC-V may be lower license fees. Apple would only pay if it bought into RISC-V International.

Some more articles:

• RISC-V CEO: Biggest opportunity to change computing since the 1980s | ZDNet
• An Open Alternative to Intel and ARM: What is RISC-V?
• Is RISC-V The Future?
• RISC-V Is On a Roll. Is It Ready to Sit Alongside Intel, AMD, and Arm?
• Is Intel Really Willing to Pay $2B+ for RISC-V Startup SiFive?
• Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip
• Ventana Micro Systems raises $38M to design datacenter RISC-V processors | VentureBeat

 

[steve_bank]

It is a risky business....

I would say one of the differences between RISK and complex is complex has a wide range of memory-cpu data transfer modes. It speeds up processing for certain types of operations. Like sortng and searching algorithms.

For example if you have to repeatedly add a constant to a number there are two simple adressing modes.

One is immediate mode. This means the number is stored as part of the operation code in memory or immediately follows the op codea, it is hard coded. It reduces the number of memory fetches.

Otherwise you have to move each addition operand from memory to a register in the cpu then execute the addition.

In a RISC chip you may have to execute more instructions to move data around in the and to memory to et somethng dome. A complex chip simply takes less instructions and less clock cyclces.

Some of the basic instructions

shift
add
subtract
multiply
loop
compare , bit OR AND
memory - cpu transfers
basic logic functions

No matter how complex the software, it all comes down to a small number of basic instructions and formal logic in a different form. It is remarkable.

RISC in the past meant smaller chips and lower costs.

I may be wrong, I recall complex parts like the 386 and beyond have been called vector processors, vector meaning lists and files. Data processing.